It is known that when the hold and setup times of flip-flops (such as D-type flip-flops) are violated, the flip-flop often enters a metastable state. Metastability can also occur when both inputs to a latch are either both 00 or 11.
Metastability can cause the latch outputs to oscillate unpredictably in a statistically known manner. While theoretically it is possible for the latch outputs to oscillate in a statistically known manner, in reality the latch will randomly shift and arrive at random output values. Such metastable values are then detected by other circuitry as different logic states.
Previous work by the instant inventor has focused on using the unpredictability, or randomness, of the metastable flip-flop, to provide a true random number generator.
FIG. 1 illustrates a random number generator comprising a latch 150 having two cross-connected NAND gates 110 and 115. The flip-flop 105 receives its clock pulse from clock oscillator 112, and the inverted output (−Q) is fed back to the D input, shaping the clock signal to square wave. The non-inverted output (Q) is then fed to delay devices 113, 114, respectively. Each of the delay devices has an output directly in series with one of the NAND gates, 110,115.
If the composition of the two NAND Gates 110,115 were exactly the same, there would be no need for the delay devices to achieve the highest frequency to get flip-flop 150 to become metastable. However, the NAND gates will ordinarily differ somewhat, and their differences (gain, offset, speed . . . ) will influence their metastability.
In addition, the difference between the NAND gates changes with temperature, supply voltage and possible environmental factors, so for the highest frequency at which the flip-flop gets metastable, one of the delays has to be tuned dynamically in very small steps. If the flip-flop gets metastable, the output signal is random. However, although the output is random, it is usually not even at a standard logic level.
FIG. 2 shows a string of conventional cascaded flip-flops 205,210,215. We know from this prior art arrangement that even these few cascaded flip-flops ensures with a very high probability that the output is in a 0 or 1 level. If the input to D in flip-flop 205 should come from a metastable flip-flop, the output of this detector is sufficiently random.
However, when one measures the random number generation speed, it is often unknown whether the optimum delay is equal to, smaller or larger than the actual delay. Thus, a complex algorithm is needed to find the highest speed and keep the circuit at this point.
With regard to FIG. 1, it is easy to see that one of the delay elements 113, 114 can be fixed to produce a signal delay equal to the median of the delay range necessary to keep the speed at a maximum. The other delay element is enough to be variable within the delay range so as to provide a large number of different delay values (typically 16-256), and can be selected by suitable codes (e.g. a binary multiplexer). However, in order to maximize such a system, there is a need for a method that dynamically tunes the delay to keep the random number generator at maximum speed.